Job Description:

RESPONSIBILITIES:

Kforce's client, a growing and established Semiconductor Company in the Austin, TX area, is seeking a Senior Analog IC Layout Designer.

Summary:
The company offers a competitive compensation package including base salary, profit sharing and stock/RSU's. We have been working with this client for many years and have placed numerous engineers there over the years. We are working directly with the Hiring Manager on this search assignment. The Senior Analog IC Layout Designer will work closely with circuit designers to generate topological custom layouts of high-performance, cutting-edge IC products. This position is hybrid remote (2 days in office & 3 days from home). This candidate must reside in the Austin, TX area, but the client is open to out of state candidates willing to relocate to the Austin, TX area.

Responsibilities will include:

• The Senior Analog IC Layout Designer will work closely with circuit designers to complete the custom physical layout and verification of high-performance analog/mixed-signal CMOS Integrated Circuits using Cadence Virtuoso XL Layout and PVS Verification tools in FinFET technologies


• Use problem solving skills, experience, and creativity to layout circuits that meet size, schedule, and performance specifications while meeting FinFET technology rules


• Run physical design verification tools to debug, improve, and verify layout blocks


• As a Senior Analog IC Layout Designer, you will collaborate with fellow team members on continuous improvement opportunities in the flow, layout techniques, and design methodologies

REQUIREMENTS:

• Associates or higher degree in Electronic/IC layout CAD specialization, engineering or related program or equivalent work experience


• At least 3-6+years of transistor level custom analog mixed signal layout design experience


• At least 2-4+ years of experience in IC layout design in FinFET technology node (Anywhere between 5 nm up to 16 nm process nodes will work)


• Strong understanding of layout fundamentals and best practices


• Solid understanding of semiconductor manufacturing process and DFM techniques


• Must be knowledgeable with CAD tools like Cadence Virtuoso XL, PVS/Calibre


• Must be familiar with Cadence Design Environment (CDE) and Unix OS


• Must have strong communication skills and be a team player


• Proficient at debugging/fixing LVS/DRC errors


• Experience with synthesis/advanced place and route tools (Innovus) a plus but not required


• Programming knowledge in skill is a plus or similar programming or scripting languages

The pay range is the lowest to highest compensation we reasonably in good faith believe we would pay at posting for this role. We may ultimately pay more or less than this range. Employee pay is based on factors like relevant education, qualifications, certifications, experience, skills, seniority, location, performance, union contract and business needs. This range may be modified in the future.

We offer comprehensive benefits including medical/dental/vision insurance, HSA, FSA, 401(k), and life, disability & ADD insurance to eligible employees. Salaried personnel receive paid time off. Hourly employees are not eligible for paid time off unless required by law. Hourly employees on a Service Contract Act project are eligible for paid sick leave.

Note: Pay is not considered compensation until it is earned, vested and determinable. The amount and availability of any compensation remains in Kforce's sole discretion unless
and until paid and may be modified in its discretion consistent with the law.

This job is not eligible for bonuses, incentives or commissions.

Kforce is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, pregnancy, sexual orientation, gender identity, national origin, age, protected veteran status, or disability status.

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