We are seeking Electrical Engineers with strong electronic backgrounds and experience in low TRL (Technology Readiness Level) development hardware and programs involving FPGAs, ASICs, CMOS, and unique PWB technologies for work on next generation disruptive technologies and developmental research systems within the Aerospace and Defense sectors.
Responsibilities:
Lead the transformation of initial concepts into advanced aerospace and defense technologies, driving development from early stages through advanced demonstration.
Develop, document, and test operational, functional, and environmental requirements for non-recurring research systems.
Design architectures for electronics at the system, subsystem, and unit levels, leveraging agile Model-Based Systems Engineering (MBSE) methods.
Perform complex trade studies, analyzing key performance parameters from concept through manufacturing.
Integrate new technologies with larger system architectures, managing impacts on interfaces, manufacturability, and system testing.
Oversee development and maintenance of tools, processes, and performance budget planning.
Lead customer engagements, modeling, analysis reviews, and lab demonstrations.
Collaborate with world-class researchers, providing independent review and support for teammates' work.
Qualifications:
Education: Bachelor of Science in Electrical Engineering or Computer Science/Engineering from an accredited institution.
Clearance: TS/SCI + Polygraph required.
Experience:
5+ years in system design, requirements development, and integration of subsystems into larger systems.
Expertise in FPGAs, ASICs, and both analog and digital design aspects.
Experience with model-based systems engineering (MBSE) in an agile environment.
Experience in new technology or product development.
Engineering leadership experience, including risk identification and mitigation.
Preferred Skills:
10+ years of experience in aerospace/defense electronics, or equivalent education and experience.
Familiarity with satellite avionics and payloads.
Experience with technologies like silicon via through-hole, intra-layer dielectric, and 3D chip technologies.
Proficiency in tools like Cameo, DOORS, SysML, or Department of Defense Architecture Framework (DoDAF).
