GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world's most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.
Summary of Role:
GLOBALFOUNDRIES is seeking an experienced Analog Design engineer to lead analog and mixed-signal of high-performance analog blocks in advanced CMOS processes such as FDSOI, FinFet and other CMOS nodes. The design consists of different types of amplifiers (high-speed, high-slew rate, etc.), SAR Analog-to-Digital converters, LDOs, etc.
As Principal Analog Design Engineer, you will provide technical direction and coordination to the design team and Identify opportunities to advance technology of analog design and participate in strategic internal analog IP development.
You will design while using early release and production ready Process Design Kits (PDKs), technology and tool enablement. You will use your design experience to design product-relevant demonstration hardware achieving industry-leading core functionality that meets or surpasses competitive technology performance. With your industry background you will provide feedback that will guide the associated Analog technology definition and design enablement needed by our customers to be successful in their product development. You will also present your results to strategic foundry customers thereby accelerating their time-to-market on GLOBALFOUNDRIES silicon.
Essential Responsibilities:
Collaborate with product management and end markets to define critical performance requirements for analog blocks for the next generation, IOT, mobile communications and automotive standards.
Design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications.
Work with Technical Team Leads in the areas of circuit design and architects from other disciplines like power management, Display, RF, etc.
Mentor Junior design Engineers whenever they are available.
Work closely with Physical Design Engineers to design IC circuit blocks.
Perform electrical verification and modifications to meet specifications.
Characterize silicon designs and/or work with external packaging and test engineers to comprehensively test enough ICs to demonstrate achievement of critical performance requirements.
Analyze characterization data and document results for sharing.
Work with design partners and customers to communicate design and technology value propositions regarding performances of the Foundry Reference Designs designed by you and the broader team.
Collaborate with innovators at research institutions and universities to push the performance envelope in related fields and future applications of the GF differentiated technology.
Manage tape out database and design collateral for the Reference Design Team
Work with designers to package reference design database to share with foundry customers
Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements, and programs
Other Responsibilities:
Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.
Required Qualifications:
Master's/PhD Degree from an Accredited University in Electrical Engineering, Solid State Physics, Science or Related Discipline
5 or More Years of Relevant Experience for PhD (ex: Design of high-performance analog blocks including SAR-ADC) using nanometer scale IC design technologies including such as Bulk, or FDSOI or FF. 8 years or more for Masters degree.
Design experience in some of the following blocks: high-speed op-amplifier and comparators, S&H, DAC, bias, bandgap, LDOs and SAR-ADC.
The position requires proficiency in using CAD tools for circuit simulation (such as Spectre from cadence), layout and physical verification tools.
Project and Tapeout Management experience
Lab test experience as part of silicon evaluation.
Minimal Travel Requirements
Language Fluency: English (Written & Verbal)
On-site work minimum 4 days a week
Preferred Qualifications:
Knowledge of analog and mixed-signal behavioral modeling such as Verilog A,.
Prior Product Design Experience with FDSOI, FinFET, and CMOS < 40nm.
Experience with calibration blocks for high-performance analog blocks.
Knowledge of key power management blocks such as DC-DC converters (buck & boost).
Experience with Tapeout PTRF Integration, Assembly & Verifications
Ability to communicate clearly, organize effectively and work with a group of designers.
Expected Salary Range
$128,100.00 - $234,500.00
The exact Salary will be determined based on qualifications, experience and location.
If you need a reasonable accommodation for any part of the employment process, please contact us by email at usaccommodations@gf.com and let us know the nature of your request and your contact information. Requests for accommodation will be considered on a case-by-case basis. Please note that only inquiries concerning a request for reasonable accommodation will be responded to from this email address.
An offer with GlobalFoundries is conditioned upon the successful completion of pre-employment conditions, as applicable, and subject to applicable laws and regulations.
GlobalFoundries is fully committed to equal opportunity in the workplace and believes that cultural diversity within the company enhances its business potential. GlobalFoundries goal of excellence in business necessitates the attraction and retention of highly qualified people. Artificial barriers and stereotypic biases detract from this objective and may be illegally discriminatory.
All policies and processes which pertain to employees including recruitment, selection, training, utilization, promotion, compensation, benefits, extracurricular programs, and termination are created and implemented without regard to age, ethnicity, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, sexual orientation, gender identity or expression, veteran status, or any other characteristic or category specified by local, state or federal law