Job Description:
Location: Goleta, CA
Salary: $100.00 USD Hourly - $105.00 USD Hourly
Description:
-
Title: FPGA/ASIC Verification Engineer
-
Location:
Goleta, CA
-
Duration: 06+ months Contract
Job Details:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related
- field, or equivalent practical experience.
- 8 years of experience with verification methodologies and languages such as UVM and
- SystemVerilog.
- Experience developing and maintaining verification test benches, test cases, and test
- environments.
- Experience in all aspects of the verification life cycle, specifically, SDF and GLS simulations
- Experience in Ethernet and SPI required
- UVM/python test development for driving VIPs and other stimulus drivers
- Generation of test components such as monitors, scoreboards, and python models
- Coverage closure and GLS bring-up and testing
Contact: bkumar@judge.com
This job and many more are available through The Judge Group. Find us on the web at www.judge.com
